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-- Company: 
-- Engineer: 
-- 
-- Create Date: 2022/08/03 21:08:51
-- Design Name: 
-- Module Name: triBuf - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY triBuf IS
  PORT (
    A : IN STD_LOGIC;
    B : IN STD_LOGIC;
    C : IN STD_LOGIC;
    ENA : IN BOOLEAN;
    ENB : IN BOOLEAN;
    ENC : IN BOOLEAN;
    BUS_OUT : OUT STD_LOGIC);
END triBuf;

ARCHITECTURE Behavioral OF triBuf IS
  SIGNAL A_OUT, B_OUT, C_OUT : STD_LOGIC;
  BEGIN
    A_OUT <= A WHEN (ENA) ELSE
      'Z';
    B_OUT <= B WHEN (ENB) ELSE
      'Z';
    C_OUT <= C WHEN (ENC) ELSE
      'Z';
    PROCESS (A_OUT) IS
    BEGIN
      BUS_OUT <= A_OUT;
    END PROCESS;
    PROCESS (B_OUT) IS
    BEGIN
      BUS_OUT <= B_OUT;
    END PROCESS;
    PROCESS (C_OUT) IS
    BEGIN
      BUS_OUT <= C_OUT;
    END PROCESS;
END Behavioral;